(1) Field of the Invention
The invention generally relates to semiconductor integrated circuit devices and, more particularly, to an output buffer used in integrated circuit (IC) device.
(2) Description of Prior Art
Output buffer or driver circuits are employed in integrated circuit devices as a means of transferring signals within a device to the input of another device. FIG. 1 shows a conventional output buffer 10, comprised of a pull-up PMOS transistor 12 and a pull-down NMOS transistor 14. PMOS transistor 12 has a source terminal (S) connected to the supply voltage VDD and a drain terminal (D) connected to both the output pin 16 and the drain terminal (D) of NMOS transistor 14. The source terminal of NMOS transistor 14 is connected to ground (GND). The output pin 16 is typically connected to the inputs of one or more CMOS device inputs. These inputs are modeled as a variable load capacitance 18 and the voltage across capacitance load 18 is depicted as VOUT. In addition, there is a parasitic capacitance 19 at the output terminal 16 associated with PMOS transistor 12 and NMOS transistor 14. The gate terminal (G) of the PMOS transistor 12 is connected to the output of a NAND gate 20. The gate terminal (G) of the NMOS transistor 14 is connected to the output of a NOR gate 22. A DATA signal is applied to one input of the NAND gate 20 and to one input of the NOR gate 22. An active low !ENABLE signal is applied to a second input of the NOR gate 22 and to the input of an INVERTER 24. The output of the INVERTER 24 is applied to a second input of the NAND gate 20.
A low logic level on the gate terminal (G) of PMOS transistor 12 will cause it to conduct from source (S) to drain (D). A high logic level on the gate terminal (G) of PMOS transistor 12 will result in a high resistance from source (S) to drain (D). A high logic level on the gate terminal (G) of NMOS transistor 14 will cause it to conduct from drain (D) to source (S) and a low logic level on the gate terminal (G) of NMOS transistor 14 will result in a high resistance from drain (D) to source (S). When a high level logic signal (approximately equal to VDD) is applied to the active-low !ENABLE input, the output of the INVERTER 24 is low (approximately equal to 0V). Under these conditions, the output of the NAND 20 (signal PU) is high and the output of the NOR 22 (signal PD) is low. This results in both PMOS and NMOS transistors 12 and 14, respectively, being turned off (high resistance from source to drain). This is known as the tri-state condition and is used to disconnect a device from the circuit thereby allowing another device to drive the output. Notice that in the tri-state condition, the DATA signal has no effect on the logic level of the output pin 16.
When a low level logic signal is applied to the active-low !ENABLE input, the output of the INVERTER 24 is high. With a high level logic DATA signal applied while the !ENABLE input is held low, the output of both NAND 20 (PU) and NOR 22 (PD) are low. PMOS transistor 12 is turned on (low source to drain resistance) and NMOS transistor 14 is turned off (high source to drain resistance). Load capacitance 18 and parasitic capacitance 19 will charge through the source to drain resistance of PMOS transistor 12 as shown in FIG. 2a. With a low level logic DATA signal applied while the !ENABLE input is held low, the output of both NAND 20 (PU) and NOR 22 (PD) are high. PMOS transistor 12 is turned off (high source to drain resistance) and NMOS transistor 14 is turned on (low source to drain resistance). Load capacitance 18 and parasitic capacitance 19 will discharge through the source to drain resistance of NMOS transistor 14 as shown in FIG. 2b. The time constant (τ) for charging and discharging of the load capacitance 18 and parasitic capacitance 19 is the product of the source to drain resistance (RSD) of the respective conducting device and the sum of the load capacitance 18 and parasitic capacitance 19:τ=RSD*(CLOAD+CPARASITIC).The output voltage (VOUT) while charging load capacitance 18 is given by:VOUT—charge(t)=VDD*(1−e−t/τ) volts,and the output voltage (VOUT) while discharging load capacitance 18 is given by:VOUT—discharge(t)=VDDe−t/τ volts.
Rise time is typically defined as the time it takes a signal to switch from 10% to 90% of the signal change. Thus, the rise time (tRISE) of this output buffer 10 would be the time it takes to change from 0.1*VDD to 0.9*VDD. The output buffer 10 fall time (tFALL) would be measured as the time it takes to change from 0.9*VDD to 0.1*VDD. It can be shown that:tRISE or tFALL=ln(9)*τ≈2.2 *τ=2.2*RSD*(CLOAD+CPARASITIC).As load capacitance 18 increases, the time constant (τ) increases, thereby increasing the rise and fall times (tRISE and tFALL, respectively). RSD may be decreased to shorten rise and fall times; this is accomplished by increasing the ratio of channel width to channel length in the PMOS and NMOS transistors, 12 and 14. This, however, adds additional parasitic capacitance 19 thereby preventing ideal improvements in transition times.
An improvement over the conventional output device of FIG. 1 is shown in FIG. 3. The output buffer 10 is connected as shown in FIG. 1, however, a pull-up current source 26 is added between the supply voltage VDD and the source (S) of the PMOS transistor 12. Similarly, a pull-down current source 28 is connected between the source (S) of the NMOS transistor 14 and the circuit common. Constant current sources are typically current mirrors understood by those skilled in the art.
Referring now to FIG. 3, with the active-low !ENABLE signal high, the output PMOS and NMOS transistors 12 and 14 will be off and the output will be in a tri-state condition. With the !ENABLE low and the DATA signal high, PMOS transistor 12 is turned on and NMOS transistor 14 is turned off. A constant current, IPU, supplied by pull-up current source 26 will charge the load capacitance 18 to the supply voltage VDD. Similarly, when a logic low level DATA signal is applied while !ENABLE is low turns on NMOS transistor 14 and turns off PMOS transistor 12. A constant current, IPD, supplied by pull-down current source 28 discharges the load capacitance 18. The current (IC) through the load capacitance 18 current is given by the equation:ICLOAD=CLoad*dVCLOAD/dt=CLoad*dVOUT/dt.Since, in either charge or discharge conditions, the current (IC) and load capacitance 18 are constant (either IPU or IPD), the change of the output voltage, VOUT, with respect to time (dVOUT/dt) must be constant. The output voltage (VOUT) rise and fall waveforms are shown in FIGS. 4a and 4b, respectively. The change of the output voltage, VOUT, with respect to time (dVOUT/dt) is the slew rate (SR). Thus the rising and falling slew rates are:SRRISE=IPU/CLoad,and,SRFALL=IPD/CLoad.Typically the pull-up and pull-down currents are designed to be equal, so:SR=ICLOAD/CLoad.This discussion ignores the effect of parasitic capacitance 19. IPU and IPD are adjusted to compensate for the additional capacitance.
The load capacitance of an output buffer is a function of the number of devices connected to the output. As more devices are connected to the output, the corresponding slew rate decreases and the rise time increases. Manufacture specifications are becoming more stringent; requiring a specific range of both slew rate and load capacitance. For example, consider the specifications below:0.4 V/ηsec≦SR≦1 V/ηsec15ρF≦CLOAD≦40ρF.The pull-up and pull-down source currents must equal:I=SR*CLOAD.The design challenge with these specifications is illustrated in FIG. 5. For a 15 ρF load, the current source must be between 6 mA and 15 mA while the current source must fall between 16 mA and 40 mA for the 40 ρF load. Unfortunately, there is no single selection of drive current that will meet the specification at both the minimum and maximum load capacitance.
Other approaches related to improving output buffer characteristics under varying capacitive loads exist. U.S. Pat. No. 5,926,651 to Johnston et al. describes a method where an output buffer slew rate is controlled by providing logic signals to the buffer circuit that switch in or out drive transistors with different current capability. The logic signals are generated by control circuitry that determines the load on the buffer based upon installed components (such as number and size of memory devices). U.S. Pat. No. 5,808,478 to Andresen discloses a method where the output buffer slew rate is varied by comparing the output voltage transition time against a reference. If the output transition time is too long, a counter is incremented and the output buffer drive current is increased. If the output transition time is too short, the counter is decremented thereby reducing the drive current. U.S. Pat. No. 6,265,913 B1 to Lee et al. teaches a method where the output buffer fall time is controlled by comparing the load capacitance against a threshold capacitance. If the load capacitance is larger than the threshold capacitance, a counter is incremented and additional output pull-down transistors are enabled to more quickly discharge the load capacitance. Conversely, if the load capacitance is less than the threshold capacitance, the counter is decremented and fewer pull-down transistors are enabled. U.S. Pat. No. 6,583,644 B2 to Shin describes a method where slew rate is controlled by comparison of input data rise time against bias voltages which vary with processing. Slew rate may be controlled for changing load capacitance; however, this must be accomplished by changing a reference voltage. This requires complicated circuitry or an external device pin. Senthinathan and Prince (Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise, Senthinathan, R. and Prince, J. L., IEEE Journal of Solid-State Circuits, Vol. 28, No. 12, December 1993.) describe an output driver where turn on of pull-up and pull-down output transistors are sequenced to control slew rate and avoid switching noise. This driver employs no feedback to detect load capacitance and is for fixed loads only.